Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection

ABSTRACT

In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

The present application is a continuation of and claims priority to U.S.patent application Ser. No. 11/006,274, filed Dec. 7, 2004, which is acontinuation of and claims priority to U.S. patent application Ser. No.10/697,365, filed Oct. 30, 2003 (now U.S. Pat. No. 6,865,501), which isa division of and claims priority to U.S. patent application Ser. No.09/930,355, filed Aug. 15, 2001 (now U.S. Pat. No. 6,671,644). Each ofthese patent applications is hereby incorporated by reference herein inits entirety.

FIELD OF THE INVENTION

This invention is related to electronic devices including computersystem chips, and in particular is concerned with improved diagnosis andisolation of faults in such devices.

BACKGROUND OF THE INVENTION

An earlier related patent application discloses clock gating in thecontext of a computer system chip with LBIST (logic built in self test)capability. This prior application is commonly assigned with the presentapplication, has an inventor in common herewith, and issued on Sep. 26,2000 as U.S. Pat. No. 6,125,465, entitled “Isolation/Removal of Faultsduring LBIST Testing”. The '465 patent is incorporated herein byreference in its entirety. The '465 patent discloses a diagnostic regimeunder which a clock signal is withheld from a functional unit of a chipwhich is known to have caused a fault. The remainder of the chip thencan be tested to determine if there are further faults in the chip.

The present inventors have recognized that additional testing regimescan be employed using clock gating and/or signal gating.

SUMMARY OF THE INVENTION

According to an aspect of the invention, a method of testing anelectronic device includes partitioning the device into segments byusing clock gating or signal gating, and identifying one of the segmentsthat is a source of a failure by selectively disabling at least one ofthe segments. The identifying of the failing segment may includeenabling the segments one-by-one (with the other segments disabled) andapplying a test to the enabled segment. Alternatively, the identifyingof the failing segment may include disabling the segments one-by-one(with the other segments enabled) while applying a test to the device asa whole.

According to another aspect of the invention, a method of testing anelectronic device includes partitioning the device into segments byusing clock gating or signal gating, identifying one of the segmentsthat is a source of a failure, and applying a diagnostic procedure tothe identified segment to determine a cause of the failure. All of thesegments may be logically independent of each other, or two or more ofthe segments may overlap each other. Numerous other aspects also areprovided.

These and other improvements are set forth in the following detaileddescription. For a better understanding of the invention with advantagesand features, refer to the description with reference to the followingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a computer system chip in whichclock gating is employed;

FIG. 2 is a block diagram that illustrates an example of signal gating;

FIG. 3 is a flow chart that illustrates a procedure for localizingfaults using clock gating or signal gating;

FIG. 4 is a block diagram showing another chip arrangement in whichclock gating is employed; and

FIG. 5 schematically illustrates overlapping segments formed bypartitioning using clock gating.

DETAILED DESCRIPTION OF THE INVENTION

The present invention includes a method that uses clock gating or signalgating to partition a failing device during test. The test results canbe used to localize the device's defect or defects to a segment orsegments on the device. Because clock and signal gating are oftenrelated to physical placement/layout of the device, this method may beused to create physical partitions for defect localization.

When a location of a failure has been refined to a particular segment,fail data collection and diagnostics can be targeted to the particularsegment, thereby reducing the amount and collection time for fail data,and also reducing the data volume, complexity, and fault set needed forsubsequent diagnostics.

For the present invention to be applied to a particular device, thedesign of the device should include appropriate clock or signal gating.Gating used may be originally included in the design, may be enhancedfrom the original design of the device, or may be designed inspecifically for diagnostic purposes. Gating for partitioning may beadded/synthesized into the design using unique algorithms to optimizediagnostic efficiency.

Segments resulting from gating, the gating to activate the segments andexpected test results for each diagnostic test application should beidentified. As used herein, diagnostic test application refers toapplying the original test (or fail portion of the original test) underdifferent gating conditions.

In accordance with the invention a device is tested. Devices that failthe test are identified. Clock and/or signal gating is then selectivelyactivated to isolate specific segments of each failed device. The gatingconfiguration (e.g., what is gated) depends on the search algorithmbeing used (e.g., a binary search).

After gating is selectively activated, an appropriate diagnostic test isapplied to each failed device. That is, each failed device is retestedusing the same test which originally indicated the device failure or aportion of the test that detects the failure. Expected good test resultsare tailored to clock gating (as described further below). The isolationof particular segments of a failed device and application of appropriatediagnostics are repeated to create a failure signature from results ofall of the diagnostic tests applied to a device. This process can beperformed in various ways to determine under which gating settings thedevice passes and fails (and produces the failure signature). Forexample, all gating permutations may be run to collect pass/fail data,or a binary search algorithm may be performed to localize the failure toa specific segment. The particular failure signature produced by thefailure is used to identify the failing segment. It may be necessary toprovide a failure-signature-to-segment map to interpret the failuresignature. Segments may also be mapped to physical entities on the chip(e.g., physical areas corresponding to the functional units).

Information regarding which segments have failed (e.g., defectlocalization information) can be used in a number of ways depending onthe application. For example, after a failing segment has beenidentified, diagnostic fail data collection and software diagnostics maybe targeted only to the particular segment identified as failing. Asanother example, after the failing segment has been identified, physicalfault isolation techniques may be targeted only to the particularfailing segment. As still another example, after the failing segment hasbeen identified, partition based binning may be performed.

FIG. 1 shows a chip 9 with a basic clock distribution and control systemin which the chip 9 is divided into a number (N) of functional units orsegments with each unit receiving system clocks from its own clockcontrol macro. As described below, FIG. 1 illustrates an example ofclock gating.

The chip 9 includes a GPTR (general purpose test register) 10 andfunctional units such as L1 cache array 11, L1 directory array 12,instruction unit 13 and execution unit 14. The functional units includelatches (not separately shown) connected into a scan chain (Scan In toScan Out). The system clock for each of the functional units 11-14 iscontrolled independently from its own unique clock control macro, ofwhich clock control macros 15, 16, 17 and 18 are shown, respectivelyconnected to functional units 11, 12, 13 and 14. The clock controlmacros 15-18 use an oscillator input 19 to generate system clocks forthe functional units, receiving the oscillator input 19 via a main clockdistribution unit 20.

A GPTR bit is applied to each of the clock macros 15-18 by the GPTR 10and is used by the respective clock control macro to stop or gate-offthe system clocks fed to functional units 11-14 when the respective GPTRbit is set to a binary “one” value. Accordingly, the chip 9 may bepartitioned into “segments” (e.g., L1 cache array 11, L1 cache directory12, instruction unit 13, instruction unit 14, etc.) using clock gating(e.g., via GPTR 10 and clock control macros 15-18).

FIG. 2 illustrates an example of signal gating between devices. In FIG.2, a first device 21 is connected to a second device 22 via a gatingcircuit 23. The devices 21, 22 may be, for example, analog, mixed signaldevices, or other devices wherein signal gating may be employed. Thegating circuit 23 includes a first transistor 24 (e.g., a p-channelMOSFET), a second transistor 25 (e.g., a p-channel MOSFET) and a thirdtransistor 26 (e.g., an n-channel MOSFET). The gating circuit 23 is inan “on” state when the gates of transistors 24 and 26 are high (e.g.,GATE₁=binary “1”) and the gate of transistor 25 is low (e.g.,GATE₂=binary “0”). The gating circuit is in an “off” state when thegates of transistors 24 and 26 are low (e.g., GATE₁=0) and the gate oftransistor 25 is high (e.g., GATE₂=1). When the gating circuit 23 is inan “on” state, the path between devices 21 and 22 is enabled, so thatthe input signal x for device 22 depends on the output y of device 21and transmission characteristics of the gating circuit 23. When thegating circuit 23 is in an “off” state, the path between the devices 21and 22 is disabled and the input x for device 22 is the Vdd signal.

FIG. 3 is a flow chart that illustrates a process 300 by which clockgating or signal gating is applied to localize faults to particularsegments or partitions of a device under test. The process 300 may beemployed, for example, to the devices of FIGS. 1 and 2, or to any otherdevices that employ appropriate clock or signal gating. With referenceto FIG. 3, at block 32 a device to be tested is provided. At block 34, atest is applied to the device (e.g., a test pattern used duringconventional manufacturing tests, a test pattern specifically designedfor the gating being employed, etc., as described further below). Atdecision block 36, it is determined whether the device under test haspassed the test or failed. If the device passes, it is considered a“good” device, as indicated at 38.

If it is determined at block 36 that the device under test fails thetest, then block 40 follows. At block 40, a gating configuration is set,based on a search algorithm. In one exemplary embodiment, each segmentis tested individually one after another (the search algorithm) bydisabling all segments except the segment under test (the gatingconfiguration). Numerous other gating configurations may be employed asdescribed below. The test then is applied with the gating configurationin place (block 42) and the results obtained with the gating applied arecompared to the expected (“good”) results (block 44). The expectedresults may be obtained, for example, by applying the same gatingconfiguration and the same test to a known good part and determining theresults obtained thereby (as described further below).

Following block 44 is a decision block 46 with three branches. Accordingto a first branch, the measured results from the device under test withthe gating configuration are not the same as the expected results.Accordingly, the fault is observable with the current gatingconfiguration, and assuming the search algorithms is not complete (e.g.,not all segments have been tested), and the process 300 loops back toblock 40. According to a second branch from block 46, the resultsobtained from the device under test match the expected results but thesearch algorithm is incomplete. Accordingly, the fault is not observableunder the current gating configuration and the process loops back toblock 40 (e.g., to test further gating configurations so that the faultmay be localized to a particular gated partition).

According to the third branch from block 46, the results obtained fromthe device under test under the current gating configuration match theexpected results and the search algorithm is complete. Accordingly, thefault is localized to a gated partition (the fault is localized to thesegment that failed at step 44 during the performance of the searchalgorithm). The process 300 ends in block 48. It is contemplated thatsteps 32-48 may be computer implemented.

The expected test results for a particular test and gating configurationcan be obtained using one or more of the following techniques. The mostappropriate technique will depend on the device design, test and faultisolation in question.

Ignore or x out observation points for the gated partition, that is,ignore latch or output pin values. This approach may minimize the amountof good machine simulation needed to determine expected results.

Create new expected results for the device under test for the gatingconfigurations to be tested.

Use the so-called “golden signature” approach. This is done by applyingthe gating configuration and test to a known good device and collectingthe resulting “golden” expects from the passing test. This approach canalso be used on a part that fails, if there is a set of test conditions(Vdd, temperature, timing) for which the part tests good. That is,collect the “golden” expected results when testing under passingconditions.

The present application may be applied to digital, analog, functional,manufacturing, at-speed, non-scan, scan, ABIST (array built-in selftest), LBIST, and other test patterns.

For example, testing can be performed using part or all of the originaltest suite for a device, although using other tests not included in theoriginal test suite is not precluded.

Patterns can be applied as they are during manufacturing tests. In somecases, it may be beneficial to use patterns that have been generatedspecifically to take advantage of the gated partitions. For example,when partitions overlap, a defect may reside in more than one partition.Manufacturing test patterns may activate more than one partition, addingcomplexity to the localization decision. If partitions do overlap, as ismore likely, the pattern set can be augmented such that each fault in anoverlap region is tested independently within each partition (as definedby clock gating settings) in which it resides. The augmented patternsneed not be run during manufacturing tests, but should be run duringdiagnostic testing.

The invention is consistent with using built-in self test schemes to runtest patterns and collect failure signatures on the fly, that is, usinga counter to initialize gating for each test and capturing passed/failedconditions in latches after each test segment.

The invention can be used to create a partitioned ABIST duringmanufacturing testing. For example, when an ABIST on a large array withfour sub-arrays fails, branching can be performed to rerun the ABISTwith clock gating activated to determine which sub array fails. In thatcase, only data from the failing sub-array would need to be collected tocreate a bit fail map.

Test generation software could be used to create diagnostic testpatterns, that is, each diagnostic test pattern could be a separate testmode generated by the test generation software. In addition, the testgeneration software could be enhanced to provide patterns that may begenerated to take advantage of gated partitions and/or to determinewhich output/observation latches to ignore during diagnostic testapplication. Test generation software diagnostics could be performedunder the specific diagnostic test mode that contains the failure,thereby reducing the CPU time and data volume associated with softwarediagnostics.

Defect localization to a gated partition or partitions provides usefuldiagnostic information in many situations. For example, the presentinvention may be applied to system design debug situations. When manydevices fail in the same way, defect localization points to a systematicproblem in design logic, circuit implementation, test pattern, testapplication, or process, such as a mask defect. Often, knowledge of theregion of the failure and the failed signature is sufficient fordesigners to debug logic or circuits or test. Mask checking within aknown region (smaller than the entire chip) can often be performed at abetter resolution without compromising turn-around time. Thus clockgating or signal gating may be useful for providing a localization ofthe fault to aid in systematic design debug.

As another example, the present invention may be applied to LBISTtester-based diagnostics. LBIST failures and failures indicated by othersignature based testing are often difficult to diagnose because theexpected results signatures have been “compressed” (e.g., via a multipleinput signature register (MISR)) and do not provide an obviousindication of what is failing. The present invention is particularlyapplicable to this type of problem. Using the “golden signature”approach to generate expected results avoids the costs and turn-aroundtime associated with extensive good machine simulation.

Another example in which the invention may be applied is fault isolationfor multiple defects. Often a single physical defect creates failurebehavior that is modeled by multiple defect models. For example, CMP(chemical mechanical polishing) underpolish can leave a small region(e.g., ten micrometers by ten micrometers) where minimum spaced wires ona metal level are shorted together. This type of defect would be modeledby several or many stuck-at or bridging defects. The present inventioncan be used to diagnose a part with this kind of defect and highlightits physical location, treating it as a single defect.

The present invention can also be used to diagnose parts with multiplephysical defects. The effectiveness of this application would depend onseveral factors, particularly on the relationships between the logicaffected by each defect. If the failures can be differentiated bypartition (i.e., the defects affect independent logic) or by testpattern (i.e., the defects are activated differently), then suchalgorithms may be tailored to better diagnose multiple defects by usingthis invention.

The present invention can also be used in connection with softwarediagnostics. When a defect location has been refined to a particularpartition or partitions, software diagnostics may be used to make adiagnostic determination. By using a test targeted to the identifiedpartition, fail data may be collected and analyzed in a more efficientmanner than an untargeted test, thereby reducing the amount of fail dataand time needed to collect the fail data. Targeting a region may alsoreduce the data volume, simulation model complexity, and fault setneeded for subsequent diagnostics.

The present invention may also be used preliminarily for physical faultisolation. When a partition (identified via the present invention)corresponds to a particular physical region on the chip, physical faultisolation, including techniques such as photon emission microscopy, canmake efficient use of defect localization. Another benefit of usingclock gating or signal gating may be to identify a set of test patternsand set of gated configurations, that provide an effective way toactivate the defect to make it observable for physical fault isolationtools, while reducing the overall circuit switching on the device.

The present invention may also be used in connection with diagnosticsfor manufacturing and yield improvement. The invention may be used in amanufacturing environment to automatically handle fail location, andfail data collection when necessary. Parts may be binned based on theirfail signature and identified segment. Defect locations for many partscan be analyzed across manufacturing parameters to identify common failsignatures, which might be indicative of common failure mechanisms, suchas circuit limited yield. The results may be used to identify the bestparts for more characterization and failure analysis. The presentinvention provides a diagnostic method that can be implemented in amanufacturing environment without severe impacts to test time and testprogram operation. In a manufacturing environment, retest and datacollection efficiencies are often compromised for lower manufacturingtest time and test program complexity. In one embodiment, a smallpattern set to support failing segment identification (called segment idpatterns) is included in the manufacturing test program. The segment idpatterns are applied during manufacturing test, if a device hassufficient functionality that patterns can exercise the device in avalid test. Additional data collection is limited to which segment idpatterns passed/failed. The test time impact is contained by applyingonly a small set of additional patterns, applying them only toappropriate chips, and collecting their results.

On the other hand, there is a great benefit to using the segment idpattern data collected during manufacturing test to bin the failingdevices, including more efficient targeting of subsequent testing, datacollection, and diagnostic resources.

The present invention is also applicable to diagnostics for analog andmixed signal devices. Clock and signal gating can be used to controlwhich circuitry receives clock or other signals. Gating can also be usedto control whether analog signals are passed from one circuit to thenext. For example, AC decoupling devices can be made gateable, as shownin FIG. 2. It may be desirable to add observation points to get the fullbenefit of this type of gating.

The present invention is also applicable to diagnostics for 3-Dstructures such as chip stacks. Suitable implementation of clock gatingmay allow defect localization in a chip stack. For example, the defectlocation in a stack chip can be found by coupling traditional multi-chipmodule diagnostic approaches to isolate the failing chip with thisinvention using clock gating. The defect location would be determined bytargeting diagnostics to the failing chip.

Moreover, some chip stack designs, including system-on-a-chip, maynaturally break into “vertical” inter-chip partitions that can bediagnosed using this invention. It would be advisable to includeappropriate gating in the chip stack design. The defect location may bedetermined by the intersection of the diagnosed “vertical” partition andintra-chip partition.

The present invention may also be employed as part of a redundancyarrangement. Clock gating and/or signal gating may be designed into apart to determine in a self-diagnostic way whether a function withredundant backup is failing, and to activate the backup unit whennecessary.

The following is an example of how the present invention may be appliedin the computer system chip illustrated in FIG. 1.

Expected test results may be provided using the “golden signature”method. A known good chip is available for the test. The expected testresults are LBIST signatures (values captured in latches and pin-outstates as are known in the art).

LBIST testing is applied to each chip. An LBIST failure is identifiedthat passes sufficient testing to make the LBIST test valid (probe melt,FLUSH, SCAN, others).

Clock (or signal) gating is then selectively activated to isolate eachof the N functional units in turn (e.g., L1 cache array 11, L1 directoryarray 12, and instruction units 13, 14). The general purpose testregister 10 is set to turn one functional unit off during each testpass. For each gating configuration, an LBIST test is applied to theknown good chip and to the failing chip. The return signatures areunloaded and compared. This procedure is continued with each functionalunit turned off in turn until the general purpose test register bit orbits needed to deactivate the failure are identified. The generalpurpose test register bit or bits can be mapped to the clock controlmacro and the functional unit that is failing, and also to physicalregions of the chip.

Following this diagnostic determination, additional test patternstargeted to the identified segment may be applied.

For example, if the failing signature was due to bad values in L1directory array latches (element 12 in FIG. 1), then bit 2 of thegeneral purpose test register 10 would be identified. With bit 2 set toprevent L1 directory array 12 from receiving the clock signal, the knowngood chip and the failing chip LBIST test signatures would match. Withthe bit 2 set to allow L1 directory array 12 to receive the clocksignal, the two LBIST test signatures would not match. This diagnosticdetermination may lead to running additional patterns targeted to thecircuitry in the L1 directory array 12 (e.g., generating a bit-failmap). This and other techniques may be employed to further diagnose thefault within the L1 directory array 12.

Another example of how the present invention may be applied isillustrated in FIG. 4. In this application, the chip is divided intosegments defined by the implementation of a clock or signal tree. Thetree fanouts create segments that can be controlled via clock or signalgates. In the following description, the application is described for aclock tree. The invention may also be applied in the same way to a chipthat includes a signal tree. The invention is also applicable to chipimplementations that require multiple clock or signal trees to partitionthe chip.

FIG. 4 is a simplified block diagram of a computer system chip 50provided in accordance with the invention. The chip 50 includes a clocksource 52 from which a clock signal is provided to chip segments 54, 56,58 and 60, respectively defined by clock gates 64, 66, 68 and 70. Thechip segments 54-60 may be, for example, the L1 cache array 11, the L1directory array 12, and the instruction units 13, 14 of FIG. 1, or anyother suitable circuitry. The clock gates 64-70 may be, for example, theclock macros 15-18 of FIG. 1, or any other suitable clock gatingmechanisms.

During manufacturing tests, the clock signal to all four segments 54-60is active. Let it be assumed that the chip 50 fails a manufacturingtest. Then, in a diagnostic mode, chip 50 is retested with all clocksactive to all four segments 54-60 to verify the failure. Thereafter, theclock signal is made active in sequence one at a time to each of thesegments 54-60.

Let it be assumed that the failure is present in segment 60. Then thetest will provide a passing result when clock gate 64 is active, clock66 is active and clock gate 68 is active, but the test will fail whenclock 70 is active, thereby localizing the defect to segment 60. Thefault isolation techniques, including diagnostic testing and datacollection can then be targeted to segment 60. In other words, if aparticular clock gate is enabled and the test fails, then the defectlocation is found to be in the chip segment which corresponds to theenabled clock gate.

As another example, if a test fails with clock gate 64 enabled andpasses with clock gates 66, 68 and 70 enabled, then the defect islocalized to segment 54. If the test fails with clock gate 66 enabledand passes with clock gate 64, 68 and 70 enabled, then the defect islocalized to segment 56. If the test fails with clock gate 68 enabledand passes with clock gate 64, 66 and 70 enabled, then the defect islocalized to segment 58. If the test fails with clock gate 70 enabledand passes with clock gates 64, 66 and 68 enabled, then the defect islocalized to segment 60.

In the example illustrated in FIG. 4, clock gating only affects outputstates within a single segment. However, for more complicated systems,more than one clock gate may affect the same output states. In FIG. 5,“cones” or areas of logic overlap between segments A and B. Logicstates, outputs and latch states in the common region 72 depend on clockpulses reaching logic in both segments A and B.

In operation, a test is performed with good machine expected results forall outputs, and segment A is enabled with segment B disabled. Then thetest is re-run and segment A is disabled with segment B enabled. Ifthere is a failure result in both cases, then the failure is somewherein the union of segments A and B. If the test fails with segment Aenabled and segment B disabled and passes with segment A disabled andsegment B enabled, then the failure is in segment A but outside ofcommon region 72. If the test passes with segment A enabled and segmentB disabled and fails with segment A disabled and segment B enabled, thenthe failure is in segment B, but outside the common region 72. If thetest passes with segment A enabled and segment B disabled and also withsegment A disabled and segment B enabled, then the failure is outsidethe union of segments A and B, or the failure is within the commonregion 72 and requires both clock gates to be enabled to produce thefailure. It may be possible to differentiate this situation by enablingthe clock gates for segments A and B and disabling the rest of thesegments of the chip.

The diagnostics provided in accordance with the invention can be courseor fine. The granularity of the partitioning can be tailored dependingon the part design and application. Fewer segments may be chosen toreduce test times for volume statistics, for a signature analysisapproach to selecting parts for fine diagnostics, and to provide acoarse region for further fault isolation. A larger number of segments,especially segments that map well to physical regions of a chip, aresuited for fine diagnostics to support physical failure analysis anddesign debug.

Efficiencies can be achieved by optimizing test generation formanufacturing tests, as well as diagnostic pattern generation, for thediagnostic method provided in accordance with this invention.

Tester based search algorithms can be used to automate the processescalled for by the present invention.

An original test (e.g., a conventional manufacturing test) can be used.No special test patterns are needed.

The present invention is applicable to wafers and modules, and is usefulfor many types of chips, design styles and applications. The presentinvention may also be extended to system or higher level diagnostics.

The foregoing description discloses only the preferred embodiments ofthe invention, and modifications of the above disclosed methods whichfall within the scope of the invention will be readily apparent to thoseof ordinary skill in the art. Accordingly, while the present inventionhas been disclosed in connection with the preferred embodiments thereof,it should be understood that other embodiments may fall within thespirit and scope of the invention as defined by the following claims.

1. A test control device adapted to: couple to an electronic device thatis adapted to be partitioned into segments by using clock gating orsignal gating; and control the electronic device to identify one of thesegments that is a source of a failure by selectively disabling at leastone of the segments.
 2. A computer system chip comprising: a testcontrol device adapted to: couple to an electronic device to be tested;partition the electronic device into a plurality of segments by usingclock gating or signal gating; and control the electronic device toidentify one of the plurality of segments that is a source of a failureby selectively disabling at least one of the plurality of segments. 3.The computer system chip of claim 2 wherein the test control device isadapted to partition the electronic device into the plurality ofsegments by using clock gating.
 4. The computer system chip of claim 2wherein the test control device is adapted to partition the electronicdevice into the plurality of segments by using signal gating.
 5. Atesting arrangement comprising: a test control device adapted to: coupleto an electronic device that is adapted to be partitioned into segmentsby using clock gating or signal gating; and control the electronicdevice to identify one of the segments that is a source of a failure byselectively disabling at least one of the segments; and a computeradapted to employ the test control device to: partition the electronicdevice into segments by using clock gating or signal gating; andidentify one of the segments that is a source of a failure byselectively disabling at least one of the segments.